ExpertTimers & Logic
Long-Interval Binary Frequency Divider
Clock the CD4060 from a 555 oscillator and compare the progressively slower binary-divided outputs.
Parts from the database
Other supplies
- breadboardCommon build supply
- 5 V supplyCommon build supply
- 10 kΩ and 68 kΩ resistorsCommon build supply
- 100 nF timing and 10 µF capacitorsCommon build supply
- 10 nF control-pin capacitorCommon build supply
- three LEDsCommon build supply
- three 1 kΩ resistorsCommon build supply
- 100 nF bypass capacitors ×2Common build supply
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Connections
- Build a 555 astable clock: pins 1/8 ground/+5 V, pin 4 high, pins 2/6 joined, 10 kΩ +5 V to pin 7, 68 kΩ pin 7 to pins 2/6, and 100 nF timing capacitor to ground. Add 10 nF from pin 5 to ground.
- CD4060 DIP-16 pin 16 +5 V, pin 8 ground, clock pin 11 from 555 pin 3, reset pin 12 low to count. Bypass pin 16 to 8.
- Use the datasheet pinout to select available counter outputs; the higher-numbered taps divide the clock more. Connect selected outputs through 1 kΩ and LEDs to ground. Do not assume every binary stage is bonded to an output.
Build steps
- Verify the 555 clock before connecting it to the divider.
- Power the CD4060 and check a lower divider output first.
- Move the LED to higher divider taps and compare blink rates.
- Briefly pull reset pin 12 high to clear the count, then return it low.
Software and firmware setup
This is a hardware-only circuit; no firmware is required.
Test your build
Lower taps change quickly; higher taps blink progressively slower. Exact blink timing follows the measured 555 clock and divider output.
Troubleshooting
- No output: check reset is low while counting and clock reaches pin 11.
- All outputs stop: reset may be floating or high.
- No high-tap blink observed: wait longer or use a lower divider tap.
Safety and limitations
5 V low-current demonstration, not a precision timer. Keep unused CMOS inputs at defined levels.
Manufacturer and platform documentation
Community Notes for This Project
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