BeginnerTimers & Logic
NAND Set/Reset Memory Latch
Build one bit of memory from two cross-coupled NAND gates with separate set and reset buttons.
Parts from the database
- SN74HC00N × 1Two gates form the latch
Other supplies
- breadboardCommon build supply
- regulated 5 V supplyCommon build supply
- two pushbuttonsCommon build supply
- two 10 kΩ pull-upsCommon build supply
- two LEDsCommon build supply
- two 1 kΩ resistorsCommon build supply
- 100 nF bypass capacitorCommon build supply
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Connections
- DIP-14 pin 14 +5 V, pin 7 ground; bypass the supply.
- Use gate 1 (inputs 1/2, output 3) and gate 2 (inputs 4/5, output 6). Cross-connect pin 3 to pin 5 and pin 6 to pin 2.
- Inputs pin 1 (SET-bar) and pin 4 (RESET-bar) each get a 10 kΩ pull-up and a button to ground.
- Show pins 3 and 6 using LEDs with 1 kΩ resistors to ground. Tie unused NAND inputs to ground.
Build steps
- Power up with buttons released; initial state may be either value.
- Press SET briefly and release; Q should remain high.
- Press RESET; Q should go low and Q-bar high.
- Do not press both controls together; that is an invalid state for this latch.
Software and firmware setup
This is a hardware-only circuit; no firmware is required.
Test your build
A brief SET or RESET press changes the stored state and the LEDs remain complementary after release.
Troubleshooting
- State will not hold: check cross-coupling pins 3→5 and 6→2.
- Random state: repair pull-ups and tie unused inputs.
- IC warms: remove power and check for supply or output shorts.
Safety and limitations
5 V logic only; do not drive motors or relays directly from HC outputs.
Manufacturer and platform documentation
Community Notes for This Project
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